The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
IC processing often utilizes a series of patterning processes to produce a plurality of IC features. Conventional processing utilizes a double patterning technique for patterning gate structures, which involves a line-cut first approach. For example, when patterning a plurality of features, a line-cut patterning process is performed, and then, an end-cut patterning process is performed. In logic areas (or static random access memory (SRAM) areas), the line-cut patterning process can form a poly gate, and the end-cut patterning process can provide poly line-end spacing control. It has been observed that the line-cut first approach provides less than desirable critical dimension uniformity. Particularly, the line-cut first approach can not guarantee on-target critical dimensions. It has been further observed that conventional patterning schemes that utilize an amorphous carbon patterning layer can sometimes lead to gate oxide punch-thru issues The present disclosure proposes an end-cut first approach, which can provide improved, direct critical dimension control during subsequent line-cut patterning processes, ensuring on-target critical dimension delivery.
Accordingly, what is needed is a method for fabricating an IC device that addresses the above stated issues.